1. Field of the Invention
The invention relates to circuit designs, and more particularly to circuit designs of operational amplifiers.
2. Description of the Related Art
An operational amplifier is a high-gain voltage amplifier with two differential inputs and a single-ended output. Two differential input terminals of an operational amplifier respectively receive a positive input voltage and a negative input voltage. The operational amplifier then amplifies a difference voltage between the positive input voltage and the negative input voltage according to a high gain to generate an output voltage at an output terminal. Because the operational amplifier has a high gain and low manufacturing costs, the operational amplifier is widely used as component circuits for performing addition and multiplication operations in consumer electronic devices, industrial computers, and science instruments.
Because the operational amplifier amplifies a difference voltage between two differential input voltages, the common mode DC voltages of the two differential input terminals for receiving the differential input voltages must be at the same level. An offset voltage occurs when the common mode DC voltages of the two differential input terminals are different. The offset voltage induces errors in the difference voltage between the two differential input voltages, and causes errors in the output voltage of the operational amplifier after the difference voltage is amplified. Thus, operational amplifier designs attempt to reduce the offset voltage, to avoid errors in the output voltage of the operational amplifier.
An offset voltage of an operational amplifier is determined by two factors. One factor is a random offset voltage caused by circuit component mismatch induced during the manufacturing process of the operational amplifier. The other factor is a systematic offset voltage caused by circuit component asymmetry induced by circuit design of the operational amplifier. The random offset voltage is reduced when the size of the circuit components of the operational amplifier is reduced. The systematic offset voltage is reduced when the circuit component asymmetry of the operational amplifier is reduced.
The offset voltage of an operational amplifier is calculated according to the following algorithm:
            σ      2        ⁡          (              V        OS            )        =                    σ        2            ⁡              (                  Δ          ⁢                                          ⁢                      V            Tp                          )              +                            β          n                          β          p                    ⁢                        σ          2                ⁡                  (                      Δ            ⁢                                                  ⁢                          V              Tn                                )                      +                  I                  2          ⁢                      β            p                              ⁢                                                                          σ                2                            ⁡                              (                                  Δ                  ⁢                                                                          ⁢                                      β                    p                                                  )                                                    β              p                                +                                                    σ                2                            ⁡                              (                                  Δβ                  n                                )                                                    β              n                                                    +                            σ          2                ⁡                  (                      Δ            ⁢                                                  ⁢                          λ              p                                )                    ⁢                        (                                    V              DSp                                      1              +                                                λ                  p                                ⁢                                  V                  DSp                                                              )                2              +                            σ          2                ⁡                  (                      Δλ            n                    )                    ⁢                                    (                                          V                DSn                                            1                +                                                      λ                    n                                    ⁢                                      V                    DSn                                                                        )                    2                .            
βp and βn are trans-conductance parameters of a differential input PMOS transistor and a load NMOS transistor, I is bias current, σ2(ΔVTp) is a square of a standard deviation of a threshold voltage of PMOS transistors, σ2(ΔVTn) is a square of a standard deviation of a threshold voltage of NMOS transistors. σ2(Δβp) is a square of a standard deviation of a trans-conductance of PMOS transistors, σ2(Δβn) is a square of a standard deviation of a trans-conductance of NMOS transistors, σ2(Δλp) is a square of a standard deviation of a channel length modulation parameter of PMOS transistors, and σ2(Δλn) is a square of a standard deviation of a channel length modulation parameter of NMOS transistors. VDSp is a drain-to-source voltage of PMOS transistors, and VDSn is a drain-to-source voltage of NMOS transistors. The third term of the equation is reduced by reducing the bias current I, the second term of the equation is reduced by extending the channel length of the NMOS transistors, and the first term of the equation is reduced by lowering circuit asymmetry. The systematic offset voltage is therefore mainly caused by the drain-to-source voltage difference ΔVDS between the two differential input PMOS transistors.
Referring to FIG. 1, a circuit diagram of a conventional operational amplifier 100 is shown. The operational amplifier 100 comprises differential input PMOS transistors 102 and 104, and load NMOS transistors 106 and 108. The size of the PMOS transistors 102 and 104 and the NMOS transistors 106 and 108 can be increased to reduce the random offset voltage. The load NMOS transistors 106 and 108, however, have different coupling relations, inducing circuit asymmetry of the operational amplifier 100, causing differences between the drain-to-source voltages of the differential input PMOS transistors 102 and 104, and inducing the systematic offset voltage. The operational amplifier 100 therefore has high offset voltage and poor performance.
Referring to FIG. 2, a circuit diagram of another conventional operational amplifier 200 is shown. The operational amplifier 200 comprises differential input PMOS transistors 202 and 204, and load NMOS transistors 206 and 208. The NMOS transistors 206 and 208 have the same coupling relations to allow the operational amplifier to have a symmetrical circuit structure. The drain-to-source voltages of the PMOS transistors 202 and 204 are therefore almost equal, reducing the offset voltage of the operational amplifier 200. In comparison to the operational amplifier 100 shown in FIG. 1, the operational amplifier 200 has lower gain due to the diode connection of the load NMOS transistors 206 and 208. An operational amplifier with a high gain and a reduced offset voltage is therefore required.